Pamukkale University
University is the guide to life
Welcome to PAU;
Prospective Student
Our Students
Our Staff
TR
Information Package & Course Catalogue
Home Page
About University
Name And Address
Acedemic Authorities
General Discription
Academic Calendar
General Admission Requirements
Recognition of Prior Learning
General Registration Procedures
ECTS Credit Allocation
Academic Guidance
Information For Students
Cost Of Living
Accommodation
Meals
Medical Facilities
Facilities for Special Needs Students
Insurance
Financial Support for Students
Student Affairs
Learning Facilities
International Programs
Language Courses
Internships
Sports Facilities and Leisure Activities
Student Associations
Practical Information for Mobile Students
Degree Programmes
FIRST CYCLE - BACHELOR'S DEGREE
FACULTY OF ECONOMICS & ADMINISTRATIVE SCIENCES
BUSINESS ADMINISTRATION DEPARTMENT
213 BUSINESS ADMINISTRATION (ENGLISH)
Course Information
Course Learning Outcomes
Course's Contribution To Program
ECTS Workload
Course Details
Print
COURSE INFORMATION
Course Code
Course Title
L+P Hour
Semester
ECTS
YBS 351
DIGITAL SYSTEMS
3 + 0
5th Semester
5
COURSE DESCRIPTION
Course Level
Bachelor's Degree
Course Type
Elective
Course Objective
The aim of this course is to introduce digital systems and their design. At the end of this course the student will be able to design and realize combinational logics according to the system needs described in a problem.
Course Content
Number Systems: Binary numbers, conversion between two different number systems. Arithmetic calculations of different number systems, BCD addition. Introduction to logic Circuits. Introduction to Combinational logic design: Binary logic, logic gates, Boolean algebra, min- terms and max-terms and their conversions, SOP and POS functions. System design optimization in two levels. Introduction to Karnough- Maps, system design samples solved using Karnough- Maps. Multilevel system design optimization. Decoder, encoder and multiplexer design samples. PLA design samples. Half –adder and full adder design samples. Subtraction samples using 2’s complement. Subtractor design. Introduction to 1-bit registers, introduction to different type of Flip-flops, SR-RS flip-flop, D flip-flop and JK flip- flop. Introduction to Shift Registers. Introduction to UP/DOWN Counter design using flip-flops, Ring and Johnson Counters.
Prerequisites
No the prerequisite of lesson.
Corequisite
No the corequisite of lesson.
Mode of Delivery
Face to Face
COURSE LEARNING OUTCOMES
1
Introduction to number systems
2
Introduction to logic circuits
3
ntroduction to logic circuit design
4
Combinational logic circuit design
5
Flip-flops and 1-bit registers
6
Designing shift registers and UP/DOWN Counters
COURSE'S CONTRIBUTION TO PROGRAM
Data not found.
ECTS ALLOCATED BASED ON STUDENT WORKLOAD BY THE COURSE DESCRIPTION
Activities
Quantity
Duration (Hour)
Total Work Load (Hour)
Course Duration (14 weeks/theoric+practical)
14
3
42
Hours for off-the-classroom study (Pre-study, practice)
14
4
56
Mid-terms
1
14
14
Final examination
1
18
18
Total Work Load
ECTS Credit of the Course
130
5
COURSE DETAILS
Select Year
All Years
This course is not available in selected semester.
Print
L+P:
Lecture and Practice
PQ:
Program Learning Outcomes
LO:
Course Learning Outcomes
{1}
##LOC[OK]##
{1}
##LOC[OK]##
##LOC[Cancel]##
{1}
##LOC[OK]##
##LOC[Cancel]##
Home Page
About University
Name And Address
Acedemic Authorities
General Discription
Academic Calendar
General Admission Requirements
Recognition of Prior Learning
General Registration Procedures
ECTS Credit Allocation
Academic Guidance
Information For Students
Cost Of Living
Accommodation
Meals
Medical Facilities
Facilities for Special Needs Students
Insurance
Financial Support for Students
Student Affairs
Learning Facilities
International Programs
Language Courses
Internships
Sports Facilities and Leisure Activities
Student Associations
Practical Information for Mobile Students
Degree Programmes